For patterning during integrated circuit fabrication in the prior art, top-down patterning using photolithography has been widely used. In such top-down patterning, photo-resist is patterned for in turn patterning an underlying target layer. However as integrated circuit dimensions are reduced to nanometers, photolithography with top-down patterning is limited because of properties of photo-resist material.
For example, line resolution and line edge roughness are limited by the large size of polymer molecules of the photo-resist material. In addition, a photo-resist structure that is tall and thin is prone to pattern collapse.
Accordingly, a bottom-up patterning technique using copolymer material has been developed as disclosed in U.S. Patent No. US 2006/0134556 to Nealey et al.
However, even with such bottom-up patterning, a technique for achieving a variety of patterning dimensions is desired. In addition, a technique for achieving dimensions smaller than possible with conventional photolithography is desired.